For communication terminal devices such as mobile-phone terminals, a Time Division Multiple Access (TDMA) system has been known, in which time slots can be set for one of an idle state, an action of reception from a base station and an action of transmission to a base station. A Global System for Mobile Communication (GSM) or Gaussian Minimum Shift Keying (GMSK) system are types of such TDMA systems in which only phase modulation is used.
Also, a system having an improved communication data transfer rate in comparison to GSM or GMSK systems has been known. As such an improved system, an Enhanced Data for GSM Evolution, or Enhanced Data for General Packet Radio Service (GPRS), (EDGE) system, in which amplitude modulation is used as well as phase modulation, has been in the spotlight recently.
A polar loop system has been known as a method to realize an EDGE system, by which after a transmit signal to be transmitted is separated into a phase component and an amplitude component, the phase and amplitude components undergo feedback-control using a phase-control loop and an amplitude-control loop respectively, and an amplifier combines the phase and amplitude components after the feedback control.
Non-patent Document 1, which is to be cited later, describes a polar loop transmitter having a phase-control loop and an amplitude-control loop and which supports an EDGE-transmit function. It is described therein that the power efficiency is a key market issue for mobile phones, and the polar loop system offers the advantage that an RF power amplifier working nearly in saturation achieves good power efficiency. Also, it is described that an additional advantage arises from the action of the RF power amplifier in saturation due to the polar loop system having a low-noise characteristic.
In addition, Non-patent Document 2, which is to be cited later, describes a polar modulation transmitter for GMSK in GSM and 8PSK in EDGE, in which the power control for ramping and modulation is conducted by controlling the collector source voltage. The implementation of AM modulation is achieved by a system very similar to that of a high-current CMOSLDO. According to a system very similar to that of such CMOSLDO, an AM control input signal is supplied to an inverting input terminal of a differential amplifier, an output signal of the differential amplifier is supplied to a gate of a P-channel MOS transistor, and a drain output of the P-channel MOS transistor is supplied to a non-inverting input terminal of the differential amplifier through a resistance-division-type negative feedback circuit. A drain output signal of the P-channel MOS transistor, which is proportional to the AM control input signal, is supplied to an RF power amplifier as a collector source voltage. Now, LDO refers to a series regulator of low dropout (output low voltage drop) as described in Non-patent Document 3, which is to be cited later.
Further, Non-patent Document 2 describes a special bias calibration technique for adjusting an input base bias of the RF power amplifier. For this purpose, a current-sensing circuit without any in-line ohmic loss leading to the deterioration in system efficiency is used. This current-sensing circuit includes: a simple current mirror having a large-size P-channel MOS transistor and a small-size P-channel MOS transistor connected in parallel for supplying a collector source voltage to the RF power amplifier; a differential amplifier; an N-channel MOS transistor; and a sensing resistance. A sense current at the small-size P-channel MOS transistor is converted into a sense voltage across the sensing resistance, and the sense voltage is amplified by a voltage amplifier. The amplified output of the voltage amplifier is compared with a bias reference value by another differential amplifier, and a comparison-output signal from the differential amplifier is supplied as a base bias for the RF power amplifier through a sample hold circuit.
On the other hand, Non-patent Document 3, which is to be cited later, describes a regulator of low dropout (output low voltage drop) including a protection circuit against an excessively large output current owing to the short circuit of a load, etc. The regulator includes a bandgap-reference-voltage generator, a first control loop of a voltage follower, and a second control loop for sensing an output current. The sensing resistance of the second control loop serves to convert the sense current proportional to the output current into a sense voltage. The sense voltage is compared with a reference voltage by a comparator. When the sense voltage is higher than the reference voltage, the transistor controlled by an output from the comparator shunts an input of an output circuit of the voltage follower. As a result, the regulator has a current-limit property of 5.3 amperes when outputting approximately 1.2 volts.
In addition, Patent Document 1, which is to be specified later, describes a restriction in the increase of the output current of a source-voltage-controlling regulator owing to the decrease in load impedance of the RF power amplifier controlled in the collector source voltage as described in Non-patent Document 2. For this purpose, a current limit circuit is connected to the source-voltage-controlling regulator. The current limit circuit includes: a small-size P-channel MOS transistor; a differential amplifier; a P-channel control MOS transistor; a reference-current source; an N-channel MOS transistor; and a P-channel MOS current mirror. The small-size P-channel MOS transistor of the current limit circuit is connected in parallel with a large-size P-channel MOS transistor of a regulator which supplies a collector source voltage to an RF power amplifier.
The sense current at the small-size transistor, which is proportional to the regulator output current pas sing through the large-size transistor, is supplied to the reference-current source and the gate of the N-channel MOS transistor through the source-drain path of the P-channel control MOS transistor controlled according to the output from the differential amplifier.
The lowering in the load impedance of the RF power amplifier increases the output current of the regulator and increases the sense current than the reference current of the reference-current source. Then, the N-channel MOS transistor is turned on, and the output current of the P-channel MOS current mirror pulls up the gates of both the large-size and small-size P-channel MOS transistors.
As a result, the output current from the regulator and the sense current decrease until the sense current conforms to the reference current. Thus, the current limit circuit connected with the source-voltage-controlling regulator of the RF power amplifier can restrict the maximum value of the collector current of the RF power amplifier to about 1.9 amperes.    Non-patent Document 1: Earl McCune, “High-Efficiency, Multi-Mode, Multi-Band Terminal Power Amplifiers”, IEEE microwave magazine, March 2005, PP. 44-55.    Non-patent Document 2: David R. Pehlke et al, “High Performce Open-Loop AM Modulator Designed for Power Control of an E-GPRS Polar Modulated Power Amplifier”, IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, PP. 569-572.    Non-patent Document 3: Oscar Moreira-Tamayo, “A High Current Low Dropout Regulator With Dual Output Stage and Dual Control Loop”, 2005 48th Midwest Symposium on Circuits and Systems, 7-10 Aug. 2005, PP. 992-995.    Patent Document 1: U.S. Pat. No. 7,193,474 B2